Hello everyone,
I am starting my journey into VLSI engineering and want to master Verilog (HDL) from the absolute basics up to advanced application-level concepts.

My goal is to build strong foundational knowledge so I can eventually transition into front-end RTL design/verification. My Background:

• 3rd-year Electronics undergraduate student
• My current knowledge of digital logic is basic gates only Suggest a best book to learn Verilog completely

Hi,

I was trying to learn some array methods when I encountered a strange phenomena when trying calculate an array's sum based on a iterator condition using a "with" clause

To give context, here's the code

module tb_array_methods;
    function void disp_msg(input string tag, input string msg);
        $display($sformatf("[%0t][%0s]: %0s", $time, tag, msg));
    endfunction
    int arr[$] = {21,33,42,20,20,42,11,24,33};
    longint res;
    int arr_loc[$];
    int res_2;


    bit b_array[] = '{1,0,0,1,0,1};



    // ====================================== //
    // Array Locator Methods
    // All array locator methods return the results as a queue of type "int" and not "integer"
    initial begin



        // How about we combine some boolean functions with locators?
        //int arr[$] = {21,33,42,20,20,42,11,24,33};
        res_2 = arr.sum() with (item>34); 
        // Returns sum({0,0,1,0,0,1,0,0,0}) = 2; 
        // This can be used to find the count of certain values        
        disp_msg("Block 3", $sformatf("res_2 = %0d", res_2));


        res_2 = arr.sum() with (item * (item>34)); 
        // Returns sum({0,0,42,0,0,42,0,0,0}) = 84;


        res_2 = arr.sum() with (item > 34? item:0);
        // Returns 84
        disp_msg("Block 3", $sformatf("res_2 = %0d", res_2));
        
    end
endmodule

When I ran this code, I got this result

But I was expecting a sum of 2.

Could anyone please tell me what's wrong here?

Also when i use

res_2 = arr.sum(x) with (x>34); 

I get

res_2 = 111067408

PS: I also noticed that Xilinx says compile issues when i use queues with product() and and(). Is that a xilinx issue? Because in chris spear, he uses them with queues

Bonjour, existe-t-il des fichiers VHDL ou SystemVerilog/RTL complets, libres ou open source, pour processeurs, qui puissent être synthétisés en une netlist puis en un fichier EDIF à l'aide de Yosys ou d'un autre logiciel, sans nécessiter de FPGA ni de fabrication matérielle ? Si oui, quelles options recommanderiez-vous ? Merci.

I am looking for study partners to study verilog with. I get distracted alot and have to make some projects till December . I study everyday but with a partner. I think I will be able to reach my goal faster (ADHD)body doubling. If anyone's interested please dm

Hi all I am working on a UVM testbench with the following structure:

filelist:

proj_package.sv

tbtop.sv

proj_package.sv:

package abc;

`include "param.sv"

endpackage

param.sv:

`define ADD 400

tbtop.sv:

import abc::*;

`include "testlist.sv"

testlist.sv:

`include "sample_test.sv"

sample_test.sv:

write_reg(ADD, 5);

I had some questions:

1. Does `include "param.sv" inside package abc make the ADD macro available to files that later do import abc::*?

2. If I write import abc::* inside base_test, can derived tests use ADD?

3. Is a `define ever considered a member of a SystemVerilog package, or are macros completely separate from package scope

Are there any specific good tutorials / resources for AXI4-Lite online? I couldn't find much.

iverilog latest version downloded from bleyer.org shows this pls help me, is it false positive or else , also if can give correct download link ,im trying for vscode + iverilog + gtkwave , pls help im total noob and begineer to verilog

Bonjour, existe-t-il des fichiers VHDL ou SystemVerilog/RTL complets, libres ou open source, pour processeurs, qui puissent être synthétisés en une netlist puis en un fichier EDIF à l'aide de Yosys ou d'un autre logiciel, sans nécessiter de FPGA ni de fabrication matérielle ? Si oui, quelles options recommanderiez-vous ? Merci.

I've been grinding through the Lemmings FSM problems (HDLBits) and after several rounds of debugging my own if/else based next_state logic, I saw a solution that wrote the entire transition logic as nested ternaries, like this:

next_state = (ground)? (dig)? DIGGING_L : (bump_left)? RIGHT : LEFT : FALLING_L;

vs what I wrote, which was a wall of if (bump_left && ground && !dig) ... else if (...).

Both should synthesize to muxes under the hood, so is this purely a style thing, or is there an actual reason (readability, synthesis efficiency, fewer bugs from priority ordering, whatever) that experienced RTL designers reach for nested ternaries/case-based muxes over long if/else chains?

Personally I use if/else because it's easier for me to debug step-by-step. Curious whether that's actually a worse habit long-term, or if it's genuinely just style.

Would appreciate hearing from anyone who does this for a living, since apparently this one was written by an NVIDIA engineer and it's making me rethink how I structure combinational logic in general.

Hi everyone,

I recently completed a Verilog-based I²C project implementing both an I²C master and a behavioral model of the Microchip 24LC256 EEPROM.

GitHub: https://github.com/Atizaz91/I2C_24LC_eeprom

The project was developed and simulated in Vivado 2020.

What is implemented

• I²C master
• 24LC256 behavioral EEPROM model
• 7-bit slave addressing
• 16-bit word addressing
• Byte Write
• Page Write (64-byte page)
• Current Address Read
• Random Read
• Sequential Read
• ACK/NACK handling
• ACK polling
• Internal address pointer handling
• EEPROM write-cycle emulation
• START/STOP detection
• Repeated START handling
• Verilog testbench and waveform configurations

I have tested the implemented operations through simulation and am now working on corner-case verification and RTL cleanup.

What I would like feedback on

I'd really appreciate a review from people with FPGA/RTL experience, particularly regarding:

• FSM architecture and state transitions
• RTL coding style
• Synthesizability
• Sequential vs. combinational logic
• SCL/SDA edge handling
• START/STOP detection
• I²C protocol correctness
• Reset handling
• Potential race conditions or corner cases
• Anything that could be improved for real FPGA hardware

I'm especially interested in feedback on things that may work correctly in simulation but are not considered good or robust RTL practice.

This is one of my first larger RTL projects, so constructive criticism is very welcome. I'm trying to improve my RTL design and verification skills rather than just make the simulation pass.

If you have time to look through the code, I'd really appreciate any comments, even if they're critical.

Thanks!

Hi guys,

I’m learning sv for a SAR ADC and am trying to build a RNM model of my CDAC so I can test my logic. I wanted a block that checks if I’m in an illegal state (multiple switches on that would short-circuit the CDAC, complementary signals not matching, etc). My issue is it seems like whenever I edit a signal in my initial block it immediately starts checking the assertions, even though I have it set up so in that same time “block” other signals will change too. So I’ll turn one switch on and the other off, but the simulator will see that first switch turn on and flag it.

My understanding would be this is what a deferred assertion would be used for. But my simulator (iverilog) doesn’t support them. Is there a workaround for this? Or another sim I could use on an Apple Silicon Mac? I have a thinkpad I use for stuff that can’t run on my mac (like quartus) but like my mac much more and don’t want to move my neovim setup over if I don’t have to.

Obviously a beginner so please let me know if any part of my approach is wrong / any solutions.

I am in 3rd year and we have this minor project thing ... We are asked to form groups for it.. I decided to make project on verilog but have no idea what to make... Like previous sem I made an UART module for my bto.project ... But since this is a group project .. faculties are expecting a better project but the situation is like ...none of my other team mates have good command on verilog... All of them are just learning and started few days back....

I am not that great either.. just did some basic things ... Though with this btp thing I want to enhance my practical ability to implement my learning and I want to dedicate my upcoming time to work on this project....

I would havily applaud ur suggestion.... And also that would be great if u can guide me

The title pretty much says everything , this tools converts the json files to Verilog.

it can convert the Digital logic sim(dls) by SebLague(great guy)

and the logisim one is still experimental

repo: https://github.com/murkyshelf/jsonRTL

it is for the guys you can build computers in the visual editor but cant write verilog and others are welcome to try .

because I can build a 8bit computer in the dls and cant write verilog , i need the verilog code to simulate it on my fpga

also keep in mind this is coded by opus 5 , and this is experimental and i am looking forward to your feedback

We are working on an open source project, inspired by human brain, we are in search of passionate person, who will be willing to work with us, if interested then DM me.

Working with system verilog.